The present invention relates generally to a method for driving a phase change memory device, and more particularly, to a technology for writing multi-level data to a phase change memory device having a phase change resistor.
Nonvolatile memory, including magnetic memory and phase change memory (PCM), has a data processing speed similar to that of volatile Random Access Memory (RAM) and conserves data even after power is turned off.
FIGS. 1a and 1b are diagrams showing a conventional phase change resistor (PCR) 4.
The PCR 4 comprises a phase change material (PCM) 2 formed between a top electrode 1 and a bottom electrode 3. A high temperature is generated in the PCM 2 when a voltage and a current are transmitted causing an electric conductive state change depending on the resistance of the PCM 2. The PCM may include AgLnSbTe. The PCM 2 includes chalcogenide having chalcogen elements (S, Se, Te) as a main ingredient, and more specifically a germanium antimonic tellurium (Ge2Sb2Te5) consisting of Ge—Sb—Te.
FIGS. 2a and 2b are diagrams showing the principle operation of the conventional PCR 4.
As shown in FIG. 2a, the PCM 2 can be crystallized when a low current less than a threshold value flows in the PCR 4. As a result, the PCM 2 is crystallized as a low resistant material.
As shown in FIG. 2b, the PCM 2 has a temperature higher than a melting point when a high current more than a threshold value flows in the PCR 4. As a result, the PCM 2 becomes amorphous as a high resistant material.
In this way, the PCR 4 is configured to store nonvolatile data which corresponds to the two resistance states. Data “1” refers to when the PCR 4 is at a low resistance state and data “0” refers to when the PCR 4 is at a high resistance state. As a result, the logic states of the two data can be stored.
FIG. 3 is a diagram showing a write operation of a conventional phase change resistant cell.
Heat is generated when current flows between the top electrode 1 and the bottom electrode 3 of the PCR 4 for a given period of time. As a result, the PCM 2 is changed to a crystalline or amorphous state depending on a temperature given to the top electrode 1 and the bottom electrode 3.
When a low current flows for a given period of time, the PCM 2 changes to a crystalline state due to low temperature heating so that the PCR 4, which is a low resistor, is at a set state. On the other hand, when a high current flows for a period of given time, the PCM 2 changes to an amorphous state due to high temperature heating so that the PCR 4, which is a high resistor, is at a reset state. A difference between two phases is represented by an electric resistance change.
A low voltage is applied to the PCR 4 for a long time to write the set state in a write mode. Conversely, a high voltage is applied to the PCR 4 for only a short time to write the reset state in the write mode.
When a write operating cycle starts in the conventional phase change memory device, new data is written to the selected phase change resistor PCR. As a result, the number of reset and set write operations increases and increases power consumption. This increase results in a degradation of cells and deterioration in a write characteristic of the cells.
Each cell included in a cell array has different process, device, and design conditions such that read current distribution for each cell is different. That is, the distribution of a set current Iset and a reset current Ireset becomes broad in comparison to a read current.
Based on a reference current Iref, some cells may have read currents that overlap with each other. As a result, some cells may fail when the reset current Ireset and the set current Iset are distinguished by a single reference current Iref and the set current Iset and the reset current Ireset overlap.